In a system using a plurality of semiconductor devices, a system that performs data transfer by transmitting a synchronization signal in parallel with data and in synchronization with the transition of the data in order to transfer data between the semiconductor devices at high speed is used. For instance, in a case where the semiconductor devices are a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) and a memory controller that controls the semiconductor memory device, a protocol such as DDR SDRAM (Double Data Rate Synchronous DRAM) is provided so that data transfer between the semiconductor devices such as the DRAM and the memory controller can be performed at high speed.
In recent years, the speed of systems using DRAM has particularly increased, and so has the transfer speed of data read/written from/to semiconductor devices constituting the systems. In a DRAM that needs to output data to a memory controller at high speed, DQS and DQSB signals are outputted from the DRAM to the memory controller as synchronization signals (data strobe signals) constituted by differential signals of normal and inverted signals when data read from the DRAM are transferred to the memory controller, and the memory controller uses these DQS and DQSB signals as signals that determine the timing at which DQ signals (data signals) from the DRAM is acquired. Because the data strobe signals are differential signals, they can be made into transmission signals having small amplitudes and resistant to external noise.
FIG. 1 shows timing relations between normal and inverted data strobe signals DQS and DQSB, i.e., signals outputted from the DRAM when read data are transferred from the DRAM to the memory controller, and the data signals DQ0, DQ1, . . . , DQm of multiple bits. The DRAM outputs DQS and DQSB, and DQ0, DQ1, . . . , DQm at the same timing. At this time, the output skew between DQS and DQSB, and DQ is standardized as tDQSQ. Further, the skew between when DQS and DQSB have changed and when the data switch to the next data is standardized as tQH. The system acquiring DQS, DQSB, and DQ0-m outputted from the DRAM delays DQS and DQSB sent from the DRAM inside the system so that it can acquire the data DQ0, DQ1, . . . , DQm. In FIG. 1, DQS and DQSB internally delayed by the memory controller receiving the data outputted from the DRAM are denoted as DQS (in) and DQSB (in). The valid period during which the data can be acquired using DQS and DQSB is a period tQH-tDQSQ. tQH is a timing at which the data switch to the next data, and it is bottlenecked by the system clock operating frequency used in data transfer between the semiconductor devices and the system. Here, the data setup time for DQS (in) and DQSB (in) is tS, and the hold time is tH. The longer tS and tH are, the larger the margin for data acquisition error becomes, however, tS and tH are bottlenecked by the clock frequency since they are bottlenecked by tDQSQ and tQH.
Patent Document 1 describes a semiconductor device capable of adjusting the slew rate of a data output signal according to an external command.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2005-182994A, which corresponds to US Patent Application Publication No. US2005/0135168A1.